1. Field of Invention
The invention relates to a TFT scan line control circuit for LCDs and, in particular, to a circuit that solve the problems of flicker and inhomogeneous brightness in LCDs.
2. Related Art
The LCD (Liquid Crystal Display) is a flat display with low power consumption. In comparison with the CRT (Cathode Ray Tube) of the sane screen size, the LCD is much smaller in its space occupation and weight. Unlike the curved screen in conventional CRTs, it has a planar display screen. With these advantages, LCDs have been widely used in various products, including palm calculators, electronic dictionaries, watches, mobile phones, notebook computers, communication terminals, display panels or even personal desktop computers. In particular, there is tendency that the TFT-LCD (Thin Film Transistor Liquid Crystal Display) is gradually replacing the low-level STN-LCD due to its superior properties in visible angles, contrast, and response time.
As shown in FIG. 1, there are liquid crystal capacitors 100 and transistors 110 disposed in an array. Scan lines 120 connect the gates 111 of the transistors 110. Data lines 130 connect the sources 112 of the transistors 110. Each liquid crystal capacitor 100 connects between a transistor 110 and a reference potential 115. Each scan line 120 imposes in order a rectangular voltage on the gate 111 of the transistor 110 at an interval of roughly a scanning time, which is a positive frame time divided by the number of scan lines. At the moment, the voltages D1, D2 and D3 are existent on the data lines 130. The corresponding charges are then stored in the crystal capacitors 100 at the intersection of the data lines 130 and each scan line 120 in order at times t1, t2, and t3. The shaded squares 140 in the drawing schematically explain the data storage of the rectangular waves on the data lines and the scan lines.
With further reference to FIG. 1, aside from the transistors 110 and the crystal capacitors 100 connected by the scan lines 120, there are also stray capacitors 116 and resistors 121. For currently available LCDs with a resolution of 1024×768, 1024×3 data lines are required, where the factor 3 accounts for the red, green and blue color signals for a point. The resistance 121 is generated by the generic resistance in thin and long wires (10 μm×12–14 in.). The resistance is about 0.35Ω/sq. The above-mentioned resistors 121 and the stray capacitors 116 definitely cause RC time delays. Therefore, even each scan line 120 is input with a rectangular wave that is steep at its edges, as shown in FIG. 2a, the voltage imposed on the gate of the first pixel transistor (composed of a transistor 111 and a liquid crystal capacitor 100) is almost invariant in its shape (FIG. 2b). However, on the n'th pixel, the voltage imposed on the gate has some shape deformation.
The voltages VGH and VGL in FIG. 3a are the maximum and minimum voltages at the gate of the first pixel. FIG. 3b shows that the starting (the transistor turned on) time and the decreasing (the transistor turned off) time of the scan line rectangular wave at the gate of the last pixel. Therefore, to respond such a change in the waveform, the usual scan line and data line produce a time difference Δt on purposes, as shown in FIG. 3c. That is, the data line has to wait until the previous scan line is turned off before it writes the data signals while the next scan line is turned on.
Since there is an unavoidable parasitic capacitor CGS between the TFT source/drain and gate and CGS is pretty large, although CGS does not generate any influence when the transistor is turned on, it does generate the charge coupling effect when the transistor is turned off after writing data into the liquid crystal capacitor CLC and a storage capacitor CS. FIG. 4 shows that the voltage at the drain of the transistor drops from VD by ΔVD to (VD−ΔVD) 142. This voltage is maintained till the end of the positive frame time, which is about 16.7 ms. The ΔVD is CGS(VGH−VGL)/(CGS+CS+CLC). To prevent decomposition of the liquid crystal from, a negative frame time (when the voltage VD is negative) has to be imposed after a frame time (when the voltage VD is positive). At this moment, the charge coupling effect due to the capacitor CGS still produces a voltage drop of ΔVD to the voltage −VD−ΔVD 144. FIG. 5 illustrates such a situation.
In the n'th pixel of the scan lines, the RC time delay deforms the square waveform of the scan line and makes the capacitor CGS generate the charge coupling effect. Therefore, the gate voltages of the n'th pixel and the first pixel are different, resulting in the flicker problem of a large TFT-LCD. To conquer the above problem, a common method is to change the IC design of the scan line driver. Nevertheless, this will increase the cost and thus is not economical at all. It is thus an object of the invention to provide an effective method that solves the above problem.